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<div class="header">
  <div class="headertitle"><div class="title">TIM Trigger Selection <div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___t_i_m.html">TIM</a> &raquo; <a class="el" href="group___t_i_m___exported___constants.html">TIM Exported Constants</a></div></div></div>
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gab7cf2b7db3956d4fd1e5a5d84f4891e7" id="r_gab7cf2b7db3956d4fd1e5a5d84f4891e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gab7cf2b7db3956d4fd1e5a5d84f4891e7">TIM_TS_ITR0</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gad90fbca297153ca9c0112a67ea2c6cb3" id="r_gad90fbca297153ca9c0112a67ea2c6cb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad90fbca297153ca9c0112a67ea2c6cb3">TIM_TS_ITR1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a></td></tr>
<tr class="memitem:ga8599ba58a5f911d648503c7ac55d4320" id="r_ga8599ba58a5f911d648503c7ac55d4320"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8599ba58a5f911d648503c7ac55d4320">TIM_TS_ITR2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a></td></tr>
<tr class="memitem:ga63183e611b91c5847040172c0069514d" id="r_ga63183e611b91c5847040172c0069514d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga63183e611b91c5847040172c0069514d">TIM_TS_ITR3</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a>)</td></tr>
<tr class="memitem:ga97923e4805e15f379eafe4fa5f09fb44" id="r_ga97923e4805e15f379eafe4fa5f09fb44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga97923e4805e15f379eafe4fa5f09fb44">TIM_TS_ITR4</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:gad0fea6ddb2a6c782a12cb7db0ce17df8" id="r_gad0fea6ddb2a6c782a12cb7db0ce17df8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad0fea6ddb2a6c782a12cb7db0ce17df8">TIM_TS_ITR5</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:ga539cd36541e24f7009713a4c48b036f0" id="r_ga539cd36541e24f7009713a4c48b036f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga539cd36541e24f7009713a4c48b036f0">TIM_TS_ITR6</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:ga5f454db2459d03ac796190f09fa75bbc" id="r_ga5f454db2459d03ac796190f09fa75bbc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5f454db2459d03ac796190f09fa75bbc">TIM_TS_ITR7</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:gab84e0eb124670693149c7f1b775fb87b" id="r_gab84e0eb124670693149c7f1b775fb87b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gab84e0eb124670693149c7f1b775fb87b">TIM_TS_ITR8</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:ga8ed963d761840dfed585f147d2cbb976" id="r_ga8ed963d761840dfed585f147d2cbb976"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8ed963d761840dfed585f147d2cbb976">TIM_TS_ITR9</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:gabfe43c9fd555ce5e726c5a879b965ecc" id="r_gabfe43c9fd555ce5e726c5a879b965ecc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabfe43c9fd555ce5e726c5a879b965ecc">TIM_TS_ITR10</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:gac97a5396aa30a45df480ccd8562ae470" id="r_gac97a5396aa30a45df480ccd8562ae470"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac97a5396aa30a45df480ccd8562ae470">TIM_TS_ITR11</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td></tr>
<tr class="memitem:ga09c956f6d06ec782aff181ac65031d70" id="r_ga09c956f6d06ec782aff181ac65031d70"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga09c956f6d06ec782aff181ac65031d70">TIM_TS_ITR12</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaccf33c88c2d65cf2bcf20dbf80f4ea60">TIM_SMCR_TS_4</a>)</td></tr>
<tr class="memitem:gac0a650df237ecf620a6b0b3d478c2186" id="r_gac0a650df237ecf620a6b0b3d478c2186"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac0a650df237ecf620a6b0b3d478c2186">TIM_TS_ITR13</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaccf33c88c2d65cf2bcf20dbf80f4ea60">TIM_SMCR_TS_4</a>)</td></tr>
<tr class="memitem:ga8c89554efc693e679c94b5a749af123c" id="r_ga8c89554efc693e679c94b5a749af123c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8c89554efc693e679c94b5a749af123c">TIM_TS_TI1F_ED</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a></td></tr>
<tr class="memitem:ga38d3514d54bcdb0ea8ac8bd91c5832b5" id="r_ga38d3514d54bcdb0ea8ac8bd91c5832b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga38d3514d54bcdb0ea8ac8bd91c5832b5">TIM_TS_TI1FP1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a>)</td></tr>
<tr class="memitem:ga0ed58a269bccd3f22d19cc9a2ba3123f" id="r_ga0ed58a269bccd3f22d19cc9a2ba3123f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0ed58a269bccd3f22d19cc9a2ba3123f">TIM_TS_TI2FP2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a>)</td></tr>
<tr class="memitem:gaece08e02e056613a882aa7ff0a6ccc2d" id="r_gaece08e02e056613a882aa7ff0a6ccc2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaece08e02e056613a882aa7ff0a6ccc2d">TIM_TS_ETRF</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a>)</td></tr>
<tr class="memitem:ga257bee9dc9f2f71a73124dd8c2329480" id="r_ga257bee9dc9f2f71a73124dd8c2329480"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga257bee9dc9f2f71a73124dd8c2329480">TIM_TS_NONE</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<a name="doc-define-members" id="doc-define-members"></a><h2 id="header-doc-define-members" class="groupheader">Macro Definition Documentation</h2>
<a id="gaece08e02e056613a882aa7ff0a6ccc2d" name="gaece08e02e056613a882aa7ff0a6ccc2d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaece08e02e056613a882aa7ff0a6ccc2d">&#9670;&#160;</a></span>TIM_TS_ETRF</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TS_ETRF&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Filtered External Trigger input (ETRF) </p>

</div>
</div>
<a id="gab7cf2b7db3956d4fd1e5a5d84f4891e7" name="gab7cf2b7db3956d4fd1e5a5d84f4891e7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab7cf2b7db3956d4fd1e5a5d84f4891e7">&#9670;&#160;</a></span>TIM_TS_ITR0</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TS_ITR0&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Internal Trigger 0 (ITR0) </p>

</div>
</div>
<a id="gad90fbca297153ca9c0112a67ea2c6cb3" name="gad90fbca297153ca9c0112a67ea2c6cb3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad90fbca297153ca9c0112a67ea2c6cb3">&#9670;&#160;</a></span>TIM_TS_ITR1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TS_ITR1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Internal Trigger 1 (ITR1) </p>

</div>
</div>
<a id="gabfe43c9fd555ce5e726c5a879b965ecc" name="gabfe43c9fd555ce5e726c5a879b965ecc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabfe43c9fd555ce5e726c5a879b965ecc">&#9670;&#160;</a></span>TIM_TS_ITR10</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TS_ITR10&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Internal Trigger 10 (ITR10) </p>

</div>
</div>
<a id="gac97a5396aa30a45df480ccd8562ae470" name="gac97a5396aa30a45df480ccd8562ae470"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac97a5396aa30a45df480ccd8562ae470">&#9670;&#160;</a></span>TIM_TS_ITR11</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TS_ITR11&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Internal Trigger 11 (ITR11) </p>

</div>
</div>
<a id="ga09c956f6d06ec782aff181ac65031d70" name="ga09c956f6d06ec782aff181ac65031d70"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga09c956f6d06ec782aff181ac65031d70">&#9670;&#160;</a></span>TIM_TS_ITR12</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TS_ITR12&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaccf33c88c2d65cf2bcf20dbf80f4ea60">TIM_SMCR_TS_4</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Internal Trigger 12 (ITR12) </p>

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<a id="gac0a650df237ecf620a6b0b3d478c2186" name="gac0a650df237ecf620a6b0b3d478c2186"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac0a650df237ecf620a6b0b3d478c2186">&#9670;&#160;</a></span>TIM_TS_ITR13</h2>

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          <td class="memname">#define TIM_TS_ITR13&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaccf33c88c2d65cf2bcf20dbf80f4ea60">TIM_SMCR_TS_4</a>)</td>
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<p>Internal Trigger 13 (ITR13) </p>

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<a id="ga8599ba58a5f911d648503c7ac55d4320" name="ga8599ba58a5f911d648503c7ac55d4320"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8599ba58a5f911d648503c7ac55d4320">&#9670;&#160;</a></span>TIM_TS_ITR2</h2>

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          <td class="memname">#define TIM_TS_ITR2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a></td>
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<p>Internal Trigger 2 (ITR2) </p>

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<a id="ga63183e611b91c5847040172c0069514d" name="ga63183e611b91c5847040172c0069514d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga63183e611b91c5847040172c0069514d">&#9670;&#160;</a></span>TIM_TS_ITR3</h2>

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          <td class="memname">#define TIM_TS_ITR3&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a>)</td>
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<p>Internal Trigger 3 (ITR3) </p>

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<a id="ga97923e4805e15f379eafe4fa5f09fb44" name="ga97923e4805e15f379eafe4fa5f09fb44"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga97923e4805e15f379eafe4fa5f09fb44">&#9670;&#160;</a></span>TIM_TS_ITR4</h2>

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          <td class="memname">#define TIM_TS_ITR4&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
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<p>Internal Trigger 4 (ITR4) </p>

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<a id="gad0fea6ddb2a6c782a12cb7db0ce17df8" name="gad0fea6ddb2a6c782a12cb7db0ce17df8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad0fea6ddb2a6c782a12cb7db0ce17df8">&#9670;&#160;</a></span>TIM_TS_ITR5</h2>

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          <td class="memname">#define TIM_TS_ITR5&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
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<p>Internal Trigger 5 (ITR5) </p>

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<a id="ga539cd36541e24f7009713a4c48b036f0" name="ga539cd36541e24f7009713a4c48b036f0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga539cd36541e24f7009713a4c48b036f0">&#9670;&#160;</a></span>TIM_TS_ITR6</h2>

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          <td class="memname">#define TIM_TS_ITR6&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
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<p>Internal Trigger 6 (ITR6) </p>

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<a id="ga5f454db2459d03ac796190f09fa75bbc" name="ga5f454db2459d03ac796190f09fa75bbc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5f454db2459d03ac796190f09fa75bbc">&#9670;&#160;</a></span>TIM_TS_ITR7</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TS_ITR7&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
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<p>Internal Trigger 7 (ITR7) </p>

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<a id="gab84e0eb124670693149c7f1b775fb87b" name="gab84e0eb124670693149c7f1b775fb87b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab84e0eb124670693149c7f1b775fb87b">&#9670;&#160;</a></span>TIM_TS_ITR8</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TS_ITR8&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
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<p>Internal Trigger 8 (ITR8) </p>

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<a id="ga8ed963d761840dfed585f147d2cbb976" name="ga8ed963d761840dfed585f147d2cbb976"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8ed963d761840dfed585f147d2cbb976">&#9670;&#160;</a></span>TIM_TS_ITR9</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TS_ITR9&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga6abf2e23327e612d1363e664bf1e1221">TIM_SMCR_TS_3</a>)</td>
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<p>Internal Trigger 9 (ITR9) </p>

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<a id="ga257bee9dc9f2f71a73124dd8c2329480" name="ga257bee9dc9f2f71a73124dd8c2329480"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga257bee9dc9f2f71a73124dd8c2329480">&#9670;&#160;</a></span>TIM_TS_NONE</h2>

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          <td class="memname">#define TIM_TS_NONE&#160;&#160;&#160;0x0000FFFFU</td>
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<p>No trigger selected </p>

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<a id="ga8c89554efc693e679c94b5a749af123c" name="ga8c89554efc693e679c94b5a749af123c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8c89554efc693e679c94b5a749af123c">&#9670;&#160;</a></span>TIM_TS_TI1F_ED</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TS_TI1F_ED&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a></td>
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<p>TI1 Edge Detector (TI1F_ED) </p>

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<a id="ga38d3514d54bcdb0ea8ac8bd91c5832b5" name="ga38d3514d54bcdb0ea8ac8bd91c5832b5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga38d3514d54bcdb0ea8ac8bd91c5832b5">&#9670;&#160;</a></span>TIM_TS_TI1FP1</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TS_TI1FP1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a>)</td>
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<p>Filtered Timer Input 1 (TI1FP1) </p>

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<a id="ga0ed58a269bccd3f22d19cc9a2ba3123f" name="ga0ed58a269bccd3f22d19cc9a2ba3123f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0ed58a269bccd3f22d19cc9a2ba3123f">&#9670;&#160;</a></span>TIM_TS_TI2FP2</h2>

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          <td class="memname">#define TIM_TS_TI2FP2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a>)</td>
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<p>Filtered Timer Input 2 (TI2FP2) </p>

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